10/20 上課結果

module top;

wire x_in1,x_in2,x_in3,x_in4;

wire y_out;

system_clock #200 clock1(x_in1);

system_clock #100 clock2(x_in2);

system_clock #50 clock3(x_in3);

system_clock #25 clock4(x_in4);

AOI_Unit m1(y_out,x_in1,x_in2,x_in3,x_in4);
endmodule

module AOI_Unit(y_out,x_in1,x_in2,x_in3,x_in4);

input x_in1,x_in2,x_in3,x_in4;

output y_out;

wire y1,y2;

and #1(y1,x_in1,x_in2);

and #1(y2,x_in3,x_in4);

nor #1(y_out,y1,y2);

endmodule

module system_clock(clk);

parameter PERIOD = 100;

output clk;

reg clk;

initial clk = 0;

always

begin

#(PERIOD/2) clk = ~clk;

#(PERIOD/2) clk = ~clk;

end

always@(posedge clk)

if($time > 1000) #(PERIOD-1)$stop;

endmodule

10/13

module top;

wire a,b;

wire sum,c_out;

system_clock #100 clock1(a);

system_clock #50 clock2(b);

Add_half AH1(sum,c_out,a,b);

endmodule

module Add_half(sum,c_out, a, b);

input a,b;

output sum,c_out;

wire c_out_bar;

xor(sum, a, b);

nand(c_out_bar, a, b);

not(c_out,c_out_bar);

endmodule

module system_clock(clk);

parameter PERIOD = 100;

output clk;

reg clk;initialclk = 0;

always

begin

#(PERIOD/2) clk = ~clk;

#(PERIOD/2) clk = ~clk;

end

always@(posedge clk)

if($time > 1000) #(PERIOD-1)$stop;

endmodule

homework

Design a verilog model of a half adder and write a
testbench to verify the designed verilog model.


p9. 半加法器設計電路
module Add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;

xor (sum,a,b);
nand (c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

第一次

module top ;
wire a,b ;
reg c ;
system_clock #100 clock1 (a) ;
system_clock #50 clock1 (b) ;
always
#1 c=a & b ;
//延遲1個時間單位//
endmodule

module system_clock (CLK) ;
parameter PERIOD = 100 ;
output CLK ;
reg CLK ;
initial
CLK=0 ;
always
begin
#(PERIOD/2) CLK=~CLK ;
#(PERIOD/2) CLK=~CLK ;
end

always @ (posedge CLK)
if ($time>1000) #(PERIOD-1)$stop ;
endmodule