12/08---位準觸發

module top;

wire enable,data;

wire q_out;

system_clock #200 clock1(enable);

system_clock #100 clock2(data);

latch abc(q_out,enable,data);

endmoduleprimitive latch(q_out,enable,data);

output q_out;

input enable,data;

reg q_out;

table

.........